Dave Pon
Fort Collins,CO
Summary
A highly accomplished and results-oriented Principal VLSI CAD Analog Methodology Engineer with extensive experience spanning the entire VLSI design cycle, from circuit design and simulation to physical design, verification, and CAD tool development. Proven ability to drive cross-functional collaboration and deliver innovative solutions that significantly improve design quality, productivity, and customer satisfaction. Possesses a unique breadth of knowledge across multiple design domains, coupled with a strong leadership record in driving convergence and influencing technical roadmaps.
Overview
25
25
years of professional experience
Work History
Principal Analog Design Methodology Engineer
Intel
01.2017 - Current
- Lead a team of 5 engineers providing first-line TFM support to over 500 analog IP design engineers across the U.S., encompassing all aspects of analog TFM across 8 process nodes
- Utilize design experience to use our TFM on real designs from IP teams to proactively find issues before the are exposed to end users
- Collaborate extensively with CAD developers and end-users to continuously improve design productivity and quality, effectively bridging the gap between design needs and tool capabilities
- Leverage a broad network across Intel to proactively identify and address design challenges, providing impactful TFM solutions that improve design quality and productivity
- Cultivate strong and trusting relationships with design teams across Intel through years of partnership and demonstrated technical expertise
Analog TFM Team Lead for Server IP teams
Intel
01.2015 - 01.2019
- Spearheaded the adoption of automation techniques from digital design flows into the analog design space, resulting in a 50% reduction in overall design effort
- Led multiple Intel-wide Working Groups focused on converging Analog Layout Automation Tools and Methodologies, achieving unprecedented levels of consistency and efficiency across the organization
- Identified a critical gap between designer needs and CAD tool capabilities, motivating a transition into TFM and a focus on improving design methodologies
- Partnered with software developers to improve layout automation tools, culminating in a presentation and 'Best of DTTC' award at Intel's internal Design & Test Technology Conference
Xeon Server Microprocessors (3 generations)
Intel/Hewlett Packard
01.2010 - 01.2015
- Led the Xeon Analog Tools and Methodology Domain, leveraging expertise in design automation to enhance analog design flows
- Collaborated with design and CAD teams to develop and deploy layout automation solutions for analog design, resulting in a 50% reduction in overall design effort
VLSI Design Engineer
Intel/Hewlett Packard
01.2000 - 01.2015
- Contributed to the design of 7 CPUs, from PA-RISC processors at HP to Itanium and Xeon processors at Intel, gaining extensive experience in all aspects of VLSI design, including schematic generation, circuit simulation, layout, performance verification, and signoff
Itanium Microprocessors (3 generations)
Intel/Hewlett Packard
01.2004 - 01.2010
- Defined and implemented the project-wide methodology for the Electrical Rule Checker (ERC) tool, ensuring design quality and consistency
- Expanded technical breadth by designing several synthesis blocks
- Solely responsible for the complete design (RTL to GDS) of one of the most complex blocks on the Itanium processor, demonstrating comprehensive VLSI design expertise
- Partnered with the CAD team to develop layout automation flows adopted by over 300 engineers
PA-RISC Microprocessors (2 generations)
Intel/Hewlett Packard
01.2000 - 01.2004
- Single-handedly designed the Launch Queue block, one of the most complex and critical blocks in the PA-RISC architecture, exceeding expectations by completing a task originally assigned to three engineers
Education
Bachelor of Science - Electrical Engineering
University Of Colorado at Boulder
Bachelor of Science - Finance
University Of Colorado at Boulder
Master of Business Administration -
Arizona State University
Master of Electrical Engineering -
Arizona State University
Skills
- VLSI Design
- Analog/Mixed-Signal (AMS) Design & Methodology
- CAD Tool Development
- Layout Automation
Timeline
Principal Analog Design Methodology Engineer
Intel
01.2017 - Current
Analog TFM Team Lead for Server IP teams
Intel
01.2015 - 01.2019
Xeon Server Microprocessors (3 generations)
Intel/Hewlett Packard
01.2010 - 01.2015
Itanium Microprocessors (3 generations)
Intel/Hewlett Packard
01.2004 - 01.2010
VLSI Design Engineer
Intel/Hewlett Packard
01.2000 - 01.2015
PA-RISC Microprocessors (2 generations)
Intel/Hewlett Packard
01.2000 - 01.2004
Bachelor of Science - Finance
University Of Colorado at Boulder
Master of Electrical Engineering -
Arizona State University
Bachelor of Science - Electrical Engineering
University Of Colorado at Boulder
Master of Business Administration -
Arizona State University
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