DANA BURGESS
Senior ASIC/FPGA Engineer
Loveland,CO
Summary
Experienced digital design engineer with 40+ years of proven success in designing, analyzing, simulating, and debugging digital systems. Most experienced with ASIC and FPGA design.
Overview
41
41
years of professional experience
4
4
years of post-secondary education
Work History
SENIOR ENGINEER
SEAKR CORP
Parker, CO
06.2023 - 11.2024
- ASIC/FPGA Design: Responsible for multiple designs for ASIC and FPGA implementation, including RTL (verilog and system verilog), simulation, synthesis, place/route
- Worked with RTG4, Virtex, and PolarFire FPGAs
- Responsible for Spyglass LINT and CDC for multiple projects
- Familiar with Microchip's Polarfire FPGAs, Libero Design Suite
- Scripting with Perl, TCL, shell, python
- Senior Engineer Duties: Participated in many design reviews, analysis, assisting different groups with design and CDC
- Was SME (Subject Matter Expert) for CDC using Synopsys Spyglass tool
SENIOR ENGINEER
SEAGATE TECHNOLOGIES
Longmont, CO
03.2022 - 06.2023
- ASIC/FPGA Design: Responsible for multiple designs for FPGA implementation, including RTL (verilog and system verilog), simulation, synthesis
- Responsible for Spyglass LINT and CDC for entire project
- Experience with LEC (formal verification)
- DDR: Lead design/implementation of Intel DDR4 controller for FPGA using Quartus system software from Intel
- Scripting with Python, Perl, TCL, shell
SENIOR ENGINEER
SEAKR CORP
Parker, CO
08.2019 - 03.2022
- ASIC/FPGA Design: Responsible for multiple designs for ASIC and FPGA implementation, including RTL (verilog and system verilog), simulation, synthesis, place/route
- Responsible for Spyglass LINT and CDC for entire project
- Experience with LEC (formal verification)
- DFT lead: Responsible for DFT implementation using Mentor Tessent flow, including design/implementation/verification of rtl modules for different functions in the chip
- Familiar with CLPI, I2C protocols
- Scripting with Perl, TCL, shell
SENIOR ENGINEER
INTEL CORP
Fort Collins, CO
02.2017 - 08.2019
- Responsible for implementing scan into existing subsystem design, which entailed removing previous scan
- Perform many different tasks including bug fixes on existing design, Spyglass CDC conformity, Spyglass DFT conformity, logic change and fixes, timing analysis, formal equivalence review
- Received recognition award for helping to implement new scan design and protocol
ASIC ENGINEER
AVAGO TECHNOLOGIES/BROADCOM
03.2006 - 11.2016
- Responsible for taking several modules from concept through synthesis, including specification, design, and simulation
- Performed physical design (place and route, test insertion, timing closure, etc) for customer designs as well as in-house modules
- Responsible for customer testbench for serdes designs
- Responsible for top level netlists for chips
- Have done formal verification and lint debugging and code changes for in-house designs
- Developed and codified the power analysis methodology for the digital portion of the serdes designs using Syopsys' primetimepx
- Solely responsible for designing and maintaining an emulator module which is used for testing serdes digital circuitry and pcie logic
- This module has gone on every test chip for the last 7 years
- Also solely responsible for designing and maintaining an emulator module which generated and tested ethernet packets for testing the mld function on chips
SENIOR ASIC DESIGNER
FREESCALE SEMICONDUCTOR
San Jose, CA
06.1996 - 01.2006
- Responsible for concept, design, testing, and synthesis of many digital modules for customer and in-house chips
- Designed and implemented a large module which interfaced between and controlled encryption logic and datapath, utilizing three separate bus interfaces in the design
- Also responsible for helping train rest of digital group in simulation testbench creation and operation
ASIC ENGINEER
FUJITSU
03.1990 - 06.1996
- Design, simulation, and synthesis of digital logic, mostly pertaining to controllers for disk drives
- Received one patent for a bus implementation on one design
ASIC ENGINEER
BULL H.N.
01.1988 - 03.1990
- Design and simulation of modules for next generation mid-size computers
ASIC ENGINEER
SIEMENS
01.1985 - 01.1988
- Design, simulation, and synthesis of modules for telecommunications devices
ENGINEER
MOTOROLA
01.1984 - 01.1985
- Design of modules for next military satellite components
Education
Bachelor of Science - Engineering
Northern Arizona University
Flagstaff, AZ 08.1980 - 05.1984
Skills
Verilog
YnthesisS
ErdiV
Primetime
Shell Scripting
Formality (synopsys)
Conformal (cadence)
Scripting (Python, Perl, TCL, shell)
Synopsys Lint/CDC
Referrals
Available upon request
Timeline
SENIOR ENGINEER
SEAKR CORP
06.2023 - 11.2024
SENIOR ENGINEER
SEAGATE TECHNOLOGIES
03.2022 - 06.2023
SENIOR ENGINEER
SEAKR CORP
08.2019 - 03.2022
SENIOR ENGINEER
INTEL CORP
02.2017 - 08.2019
ASIC ENGINEER
AVAGO TECHNOLOGIES/BROADCOM
03.2006 - 11.2016
SENIOR ASIC DESIGNER
FREESCALE SEMICONDUCTOR
06.1996 - 01.2006
ASIC ENGINEER
FUJITSU
03.1990 - 06.1996
ASIC ENGINEER
BULL H.N.
01.1988 - 03.1990
ASIC ENGINEER
SIEMENS
01.1985 - 01.1988
ENGINEER
MOTOROLA
01.1984 - 01.1985
Bachelor of Science - Engineering
Northern Arizona University
08.1980 - 05.1984